- Broadcom Inc. is an American multinational designer, developer, manufacturer, and global supplier of a wide range of semiconductor and infrastructure software products. Broadcom's product offerings serve the data center, networking, software, broadband, wireless, storage, and industrial markets
Broadcom Inc is hiring for Electrical Engineer
The job you are looking for is no longer available..- Company Name
- Broadcom Inc
- Company Website
- https://www.broadcom.com/
- Job Role
- Electrical Engineer
- Job Type
-
- Experienced
- Job Location
-
- Bengaluru/Bangalore
- Education
-
- BE/BTech
- ME/M.Tech
- Branch
-
- Electrical and Electronics Engineering
- Electromechanics Engineering
- Electrical Engineering
- Job will expire on
- 05 Aug 2023
About Company
Eligibility Criteria
- BE/BTech ME/MTech
Job Description
- Broadcom Central Engineering team is looking for a Mutiskilled PNR, STA, DFT Engineer. The Successful candidate will work in one or more domains of RTL, to GDS2 flow with end to end ownership that includes Place and Route, STA for Complex Memory, IO subsystems, ARM processor Blocks including BIST. It is great Opportunity and challenging role for the people who wants to gain in depth knowledge on end to end Chip development flow from RTL to GDS2 that includes PNR, STA, DFT insertion, Physical Verification and Signoff.
- Synthesis Constraints Review with RTL teams, DFT Insertion, PNR, STA sign off for ARM-Blocks, Memory Digital Subsystems including Tessent DFT for 5FF, and below technologies. Automation for Complex Digital subsystems, Static timing analysis, Cross Clock Domain checks, Power/Timing /EM-IR sign off. Define the Floor Plan/placement/routing/Timing constraints in ICC for Complex blocks including BIST to achieve correct by construct DRC/LVS and timing closure Define and standardize STA recipe by interacting with BUs/Central Recipe team to drive Seamless timing closure for broader subsystems. Interact with the Cross functional IP teams, Flow teams, (Synthesis/STA/DNE) to close the loop in timing violations/DRC/LVS. ICC/Synthesis/STA constraints automation to achieve predictable timing closure correct by construct DRC/LVS through automation with minimal randomness.
- Hands on Experience with Synthesis, ICC2, Fusion, Innovus, Prime time tools Hands on experience in defining ICC2/Synthesis constraints that meets timing closure needs In-depth knowledge of Signal and Power Floor plan with minimal EM/IR violations In-depth expertise with all ICC2/STA options to handle de-ratings, Options to reduce cross talk Hands on expertise with TCL/PERL to automate the end to end PNR/STA flow. Experience to handle a complex Netlist with multiple frequency domains and ICC timing closure. Hands on experience in analyzing and correlating STA .vs. ICC timing reports.
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