Cadence is a pivotal leader in electronics and system design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to complete systems for the most dynamic market applications, including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial and healthcare. For eight years in a row, Fortune magazine has named Cadence one of the 100 Best Companies to Work For.
Cadence Recruitment Drive 2025 | Cadence Hiring Electrical/Eletronics Engineer
The job you are looking for is no longer available..- Company Name
- Cadence
- Company Website
- http://www.cadence.com/
- Job Role
- Sr Principle Design Engineer
- Job Type
-
- Experienced
- Job Location
-
- Noida
- Bengaluru/Bangalore
- Pune
- Ahmedabad
- Skills
-
- Good Communication Skill
- Education
-
- ME/M.Tech
- BE/BTech
- Branch
-
- Electrical and Electronics Engineering
- Electrical Engineering
- Job will expire on
- 14 Feb 2025
About Company
Eligibility Criteria
- BE/B.Tech/ME/M.Tech - Electrical / Electronics / VLSI with experience as a design and verification engineer, with a large portion of the recent work experience on RTL design and development.
- RTL Design using Verilog is a must.
- System Verilog experience and experience with UVM based environment usage / debugging is required.
- AXI3/4 experience is desired.
- DDR Memory controller and protocol experience is highly desirable. Prior experience in RTL design and implementation of complex protocols is a must.
- Prior experience in IP development teams would be an added advantage.
Job Description
- RTL Design Engineer for DDR Memory Controller IP development team.
- The role would include the design and support of the RTL of the DDR Memory Controller solution of Cadence. All leading DDR memory protocols will be supported – including DDR4/LPDDR4.
- The work involved will be working with the existing RTL, the addition of new features into the RTL, ensuring various customer configurations are clean as part of verification regressions, supporting customers, ensuring the design is clean for LINT and CDC design guidelines.
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