- As a member of our ASIC backend/timing team, you'll be working on product designs, focusing on such tasks as clocks, timing convergence, chip layout planning, design optimization and automation of work flows. Specifically you'll be focusing on full chip layout planning (partitioning, planning clock distribution and other structures, methodology), full chip timing closure signoff (using tools such as Synopsys Primetime, Cadence Tempus etc.), design optimization, and gate-level design of high-speed logic. In this role you will also interface with architecture, rtl design, layout implementation, methodology and custom design teams to drive design implementation, timing analysis/closure all the way from micro-architecture to tape-out.
Nvidia Computer systems for Design Engineer - Electrical, Computer Science
- Company Name
- Nvidia Computer systems design services company
- Company Website
- https://www.nvidia.com/Download/index.aspx
- Experience
- 3+ Years
- Job Role
- Design Engineer - Electrical, Computer Science
- Job Type
-
- Experienced
- Job Location
-
- Bengaluru/Bangalore
- Education
-
- BE/BTech
- Branch
-
- Electronics and Telecommunication
- IT
- CS
- Electrical Engineering
About Company
Job Description
- Develop and enhance timing analysis/signoff work flow from frontend (pre-layout) to backend (post-layout) at both chip and block level.
- Chip level Integration, physically partitioning and floor planning.
- Develop custom timing scripts using tcl/primetime for clock skew analysis, special circuits such as clock dividers, core logic <-> IO macros interfaces such as PCI-E, Frame-Buffer/Memory, HDMI, etc.
- Design optimization and timing convergence related tasks.
- Development of PD work flows.
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