- We are Silicon Labs. We are the leading provider of silicon, software and solutions for a smarter, more connected world. We hire the most innovative talent in the world to solve the industry’s toughest problems, providing our customers with significant advantages in performance, energy savings, connectivity and design simplicity. Silicon Labs’ software and mixed signal engineering teams create solutions for customers in diverse markets including the Internet of Things, (IoT), internet infrastructure, TV tuners, as well as automotive and consumer radios. Our solutions are in products from the market leaders in home automation, electric vehicles, green technology, smart TVs and home voice control automation. We take pride in our products and in our people, and that’s one of the many reasons we continue to be awarded Most Respected Public Semiconductor Company by the Global Semiconductor Alliance
Silicon Labs is hiring for CAD Engineer
- Company Name
- Silicon Labs
- Company Website
- https://www.silabs.com/
- Experience
- 5+ years
- Job Role
- CAD Engineer I
- Job Type
-
- Experienced
- Job Location
-
- Hyderabad
- Skills
-
- Python
- Perl
- Education
-
- ME/M.Tech
About Company
Eligibility Criteria
- Ideal candidate should have 5+ years of experience in Physical Verification,preferably writing from scratch and/or modifying existing DRC, LVS, ERC and Dummy fill decks using industry standard tools like Mentor Calibre
- Strong debug experience reviewing LVS and DRC errors
- Strong programming skills in Perl, Python, Tcl and Shell scripting and experience in stitching together PV flows
- Experience with Cadence Virtuoso layout editor, Calibre RVE, DRV etc
- Experience with Layout Parasitic Extraction (LPE) tools like Cadence QRC or Star-RCXT
- Experience with Mentor PERC (Programmable Electrical Rule Checker) for Current Density and latchup checks is a definite plus
- Ability to work independently, drive decision-making, strong communication, and documentation skills are critical
- Familiarity with Analog and Digital design engineering concepts
- Excellent documentation and communication skills. Familiarity with Jira and Confluence is a plus
- Conduct impact analysis meetings with key stakeholders
- Familiarity with leading version control tools like Perforce, Cliosoft, Methodics will be a plus
- Familiarity working with foundry teams both internal and external to seek clarification, submit
Job Description
- Ideal candidate should have 5+ years of experience in Physical Verification,preferably writing from scratch and/or modifying existing DRC, LVS, ERC and Dummy fill decks using industry standard tools like Mentor Calibre
- Strong debug experience reviewing LVS and DRC errors
- Strong programming skills in Perl, Python, Tcl and Shell scripting and experience in stitching together PV flows
- Experience with Cadence Virtuoso layout editor, Calibre RVE, DRV etc
- Experience with Layout Parasitic Extraction (LPE) tools like Cadence QRC or Star-RCXT
- Experience with Mentor PERC (Programmable Electrical Rule Checker) for Current Density and latchup checks is a definite plus
- Ability to work independently, drive decision-making, strong communication, and documentation skills are critical
- Familiarity with Analog and Digital design engineering concepts
- Excellent documentation and communication skills. Familiarity with Jira and Confluence is a plus
- Conduct impact analysis meetings with key stakeholders
- Familiarity with leading version control tools like Perforce, Cliosoft, Methodics will be a plus
- Familiarity working with foundry teams both internal and external to seek clarification, submit
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